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MC10EP105, MC100EP105 3.3V / 5V ECL Quad 2-Input Differential AND/NAND
The MC10/100EP105 is a quad 2-input differential AND/NAND gate. Each gate is functionally equivalent to the EP05 and LVEL05 devices. With AC performance much faster than the LVEL05 device, the EP105 is ideal for applications requiring the fastest AC performance available. The 100 Series contains temperature compensation.
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* 275 ps Typical Propagation Delay * Maximum Frequency > 3 GHz Typical * PECL Mode Operating Range: VCC = 3.0 V to 5.5 V *
with VEE = 0 V NECL Mode Operating Range: VCC = 0 V with VEE = -3.0 V to -5.5 V Open Input Default State
LQFP-32 FA SUFFIX CASE 873A
MARKING DIAGRAM*
MCxxx EP105 AWLYYWW 32 1 = 10 or 100 = Assembly Location = Wafer Lot = Year = Work Week
* * Safety Clamp on Inputs
xxx A WL YY WW
*For additional information, see Application Note AND8002/D
ORDERING INFORMATION
Device MC10EP105FA MC10EP105FAR2 MC100EP105FA MC100EP105FAR2 Package LQFP-32 LQFP-32 LQFP-32 LQFP-32 Shipping 250 Units/Tray 2000 Tape & Reel 250 Units/Tray 2000 Tape & Reel
(c) Semiconductor Components Industries, LLC, 2002
1
September, 2002 - Rev. 8
Publication Order Number: MC10EP105/D
MC10EP105, MC100EP105
D0b D1a D1a D1b D1b D2a D2a D2b
D0a D0a D0b 16 15 14 D2b D3a D3a VCC D3b D3b VEE NC D0b D1a D1a D1b D1b D2a D2a D2b D2b D3a D3a D3b D3b
Q0 Q0
24 D0b D0a D0a VEE Q0 Q0 VCC VCC 25 26 27 28 29 30 31 32 1
23
22
21
20
19
18
17
Q1 Q1
MC10EP105 MC100EP105
13 12 11 10 9
Q2 Q2
2
3
4
5
6
7
8
Q3 Q3
VCC Q1
Q1
Q2
Q2
Q3
Q3
VCC VEE
Warning: All VCC and VEE pins must be externally connected to Power Supply to guarantee proper operation.
Figure 1. 32-Lead LQFP Pinout (Top View)
Figure 2. Logic Diagram
PIN DESCRIPTION
PIN Dna*, Dnb*, Dna*, Dnb* Qn, Qn VCC VEE NC FUNCTION ECL Data Inputs ECL Data Outputs Positive Supply Negative Supply No Connect
TRUTH TABLE
Dna L L H H Dnb L H L H Dna H H L L Dnb H L H L Qn L L L H Qn H H H L
* Pins will default LOW when left open.
ATTRIBUTES
Characteristics Internal Input Pulldown Resistor Internal Input Pullup Resistor ESD Protection Human Body Model Machine Model Charged Device Model Value 75 kW N/A > 4 kV > 100 V > 2 kV Level 2 Oxygen Index: 28 to 34 UL-94 V-0 @ 0.125 in 444 Devices
Moisture Sensitivity (Note 1) Flammability Rating Transistor Count Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test 1. For additional information, see Application Note AND8003/D.
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MC10EP105, MC100EP105
MAXIMUM RATINGS (Note 2)
Symbol VCC VEE VI Iout IBB TA Tstg JA JC Tsol Parameter PECL Mode Power Supply NECL Mode Power Supply PECL Mode In ut Voltage Input NECL Mode Input Voltage Output Current VBB Sink/Source Operating Temperature Range Storage Temperature Range Thermal Resistance (Junction-to-Ambient) Thermal Resistance (Junction-to-Case) Wave Solder 0 LFPM 500 LFPM std bd < 2 to 3 sec @ 248C 32 LQFP 32 LQFP 32 LQFP Condition 1 VEE = 0 V VCC = 0 V VEE = 0 V VCC = 0 V Continuous Surge VI VCC VI VEE Condition 2 Rating 6 -6 6 -6 50 100 0.5 -40 to +85 -65 to +150 80 55 12 to 17 265 Units V V V V mA mA mA C C C/W C/W C/W C
2. Maximum Ratings are those values beyond which device damage may occur.
10EP DC CHARACTERISTICS, PECL VCC = 3.3 V, VEE = 0 V (Note 3)
-40C Symbol IEE VOH VOL VIH VIL VIHCMR IIH IIL Characteristic Power Supply Current Output HIGH Voltage (Note 4) Output LOW Voltage (Note 4) Input HIGH Voltage (Single-Ended) Input LOW Voltage (Single-Ended) Input HIGH Voltage Common Mode Range (Differential) (Note 5) Input HIGH Current Input LOW Current 0.5 Min 45 2165 1365 2090 1365 2.0 Typ 58 2290 1490 Max 75 2415 1615 2415 1690 3.3 150 0.5 Min 45 2230 1430 2155 1460 2.0 25C Typ 59 2355 1555 Max 75 2480 1680 2480 1755 3.3 150 0.5 Min 45 2290 1490 2215 1490 2.0 85C Typ 60 2415 1615 Max 75 2540 1740 2540 1815 3.3 150 Unit mA mV mV mV mV V A A
NOTE: EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained. 3. Input and output parameters vary 1:1 with VCC. VEE can vary +0.3 V to -2.2 V. 4. All loading with 50 to VCC-2.0 volts. 5. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal.
10EP DC CHARACTERISTICS, PECL VCC = 5.0 V, VEE = 0 V (Note 6)
-40C Symbol IEE VOH VOL VIH VIL VIHCMR IIH IIL Characteristic Power Supply Current Output HIGH Voltage (Note 7) Output LOW Voltage (Note 7) Input HIGH Voltage (Single-Ended) Input LOW Voltage (Single-Ended) Input HIGH Voltage Common Mode Range (Differential) (Note 8) Input HIGH Current Input LOW Current 0.5 Min 45 3865 3065 3790 3065 2.0 Typ 58 3990 3190 Max 75 4115 3315 4115 3390 5.0 150 0.5 Min 45 3930 3130 3855 3130 2.0 25C Typ 59 4055 3255 Max 75 4180 3380 4180 3455 5.0 150 0.5 Min 45 3990 3190 3915 3190 2.0 85C Typ 60 4115 3315 Max 75 4240 3440 4240 3515 5.0 150 Unit mA mV mV mV mV V A A
NOTE: EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained. 6. Input and output parameters vary 1:1 with VCC. VEE can vary +2.0 V to -0.5 V. 7. All loading with 50 to VCC-2.0 volts. 8. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal.
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MC10EP105, MC100EP105
10EP DC CHARACTERISTICS, NECL VCC = 0 V, VEE = -5.5 V to -3.0 V (Note 9)
-40C Symbol IEE VOH VOL VIH VIL VIHCMR IIH IIL Characteristic Power Supply Current Output HIGH Voltage (Note 10) Output LOW Voltage (Note 10) Input HIGH Voltage (Single-Ended) Input LOW Voltage (Single-Ended) Input HIGH Voltage Common Mode Range (Differential) (Note 11) Input HIGH Current Input LOW Current 0.5 Min 45 -1135 -1935 -1210 -1935 VEE+2.0 Typ 58 -1010 -1810 Max 75 -885 -1685 -885 -1610 0.0 150 0.5 Min 45 -1070 -1870 -1145 -1870 VEE+2.0 25C Typ 59 -945 -1745 Max 75 -820 -1620 -820 -1545 0.0 150 0.5 Min 45 -1010 -1810 -1085 -1810 VEE+2.0 85C Typ 60 -885 -1685 Max 75 -760 -1560 -760 -1485 0.0 150 Unit mA mV mV mV mV V A A
NOTE: EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained. 9. Input and output parameters vary 1:1 with VCC. 10. All loading with 50 to VCC-2.0 volts. 11. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal.
100EP DC CHARACTERISTICS, PECL VCC = 3.3 V, VEE = 0 V (Note 12)
-40C Symbol IEE VOH VOL VIH VIL VIHCMR IIH IIL Characteristic Power Supply Current Output HIGH Voltage (Note 13) Output LOW Voltage (Note 13) Input HIGH Voltage (Single-Ended) Input LOW Voltage (Single-Ended) Input HIGH Voltage Common Mode Range (Differential) (Note 14) Input HIGH Current Input LOW Current 0.5 Min 45 2155 1355 2075 1355 2.0 Typ 59 2280 1480 Max 75 2405 1605 2420 1675 3.3 150 0.5 Min 45 2155 1355 2075 1355 2.0 25C Typ 62 2280 1480 Max 75 2405 1605 2420 1675 3.3 150 0.5 Min 45 2155 1355 2075 1355 2.0 85C Typ 64 2280 1480 Max 75 2405 1605 2420 1675 3.3 150 Unit mA mV mV mV mV V A A
NOTE: EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained. 12. Input and output parameters vary 1:1 with VCC. VEE can vary +0.3 V to -2.2 V. 13. All loading with 50 to VCC-2.0 volts. 14. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal.
100EP DC CHARACTERISTICS, PECL VCC = 5.0 V, VEE = 0 V (Note 15)
-40C Symbol IEE VOH VOL VIH VIL VIHCMR IIH IIL Characteristic Power Supply Current Output HIGH Voltage (Note 16) Output LOW Voltage (Note16) Input HIGH Voltage (Single-Ended) Input LOW Voltage (Single-Ended) Input HIGH Voltage Common Mode Range (Differential) (Note 17) Input HIGH Current Input LOW Current 0.5 Min 45 3855 3055 3775 3055 2.0 Typ 59 3980 3180 Max 75 4105 3305 4120 3375 5.0 150 0.5 Min 45 3855 3055 3775 3055 2.0 25C Typ 62 3980 3180 Max 75 4105 3305 4120 3375 5.0 150 0.5 Min 45 3855 3055 3775 3055 2.0 85C Typ 64 3980 3180 Max 75 4105 3305 4120 3375 5.0 150 Unit mA mV mV mV mV V A A
NOTE: EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained. 15. Input and output parameters vary 1:1 with VCC. VEE can vary +2.0 V to -0.5 V. 16. All loading with 50 to VCC-2.0 volts. 17. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal.
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MC10EP105, MC100EP105
100EP DC CHARACTERISTICS, NECL VCC = 0 V, VEE = -5.5 V to -3.0 V (Note 18)
-40C Symbol IEE VOH VOL VIH VIL VIHCMR IIH IIL Characteristic Power Supply Current Output HIGH Voltage (Note 19) Output LOW Voltage (Note 19) Input HIGH Voltage (Single-Ended) Input LOW Voltage (Single-Ended) Input HIGH Voltage Common Mode Range (Differential) (Note 20) Input HIGH Current Input LOW Current 0.5 Min 45 -1145 -1945 -1225 -1945 VEE+2.0 Typ 59 -1020 -1820 Max 75 -895 -1695 -880 -1625 0.0 150 0.5 Min 45 -1145 -1945 -1225 -1945 VEE+2.0 25C Typ 62 -1020 -1820 Max 75 -895 -1695 -880 -1625 0.0 150 0.5 Min 45 -1145 -1945 -1225 -1945 VEE+2.0 85C Typ 64 -1020 -1820 Max 75 -895 -1695 -880 -1625 0.0 150 Unit mA mV mV mV mV V A A
NOTE: EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained. 18. Input and output parameters vary 1:1 with VCC. 19. All loading with 50 to VCC-2.0 volts. 20. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal.
AC CHARACTERISTICS VCC = 0 V; VEE = -3.0 V to -5.5 V or VCC = 3.0 V to 5.5 V; VEE = 0 V (Note 21)
-40C Symbol fmax tPLH, tPHL tSKEW tJITTER VPP tr tf Characteristic Maximum Frequency (See Figure 3 Fmax/JITTER) Propagation Delay to Output Differential Within Device Skew Device to Device Skew (Note 22) Cycle-to-Cycle Jitter (See Figure 3 Fmax/JITTER) Input Voltage Swing (Differential) Output Rise/Fall Times (20% - 80%) Q 150 100 175 Min Typ >3 250 10 0.2 800 150 325 50 <1 1200 200 150 120 200 Max Min 25C Typ >3 275 10 0.2 800 170 350 50 <1 1200 220 150 150 225 Max Min 85C Typ >3 300 15 0.2 800 200 375 50 <1 1200 250 Max Unit GHz ps ps ps mV ps
21. Measured using a 750 mV source, 50% duty cycle clock source. All loading with 50 to VCC-2.0 V. 22. Skew is measured between outputs under identical transitions. 1000 900 800 VOUTpp (mV) 700 600 500 400 300 200 100 0 (JITTER) 10 9 8 7 6 5 4 3 2 1 4000 5000 JITTEROUT ps (RMS)
0
1000
2000
3000
FREQUENCY (MHz)
Figure 3. Fmax/Jitter
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EE EE EE
EEEEEEEEEE EEEEEEEEEE
MC10EP105, MC100EP105
Q Driver Device Q 50 50
D Receiver Device D
VTT VTT = VCC - 2.0 V
Figure 4. Typical Termination for Output Driver and Device Evaluation (See Application Note AND8020 - Termination of ECL Logic Devices.)
Resource Reference of Application Notes
AN1404 AN1405 AN1406 AN1504 AN1568 AN1650 AN1672 AND8001 AND8002 AND8009 AND8020
- - - - - - - - - - -
ECLinPS Circuit Performance at Non-Standard VIH Levels ECL Clock Distribution Techniques Designing with PECL (ECL at +5.0 V) Metastability and the ECLinPS Family Interfacing Between LVDS and ECL Using Wire-OR Ties in ECLinPS Designs The ECL Translator Guide Odd Number Counters Design Marking and Date Codes ECLinPS Plus Spice I/O Model Kit Termination of ECL Logic Devices
For an updated list of Application Notes, please see our website at http://onsemi.com.
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MC10EP105, MC100EP105
PACKAGE DIMENSIONS
LQFP FA SUFFIX 32-LEAD PLASTIC PACKAGE CASE 873A-02 ISSUE A
A
32 4X 25
A1
0.20 (0.008) AB T-U Z
1
-T- B B1
8
-U- V P DETAIL Y
17
AE
V1 AE DETAIL Y
9
-Z- 9 S1 S
4X
0.20 (0.008) AC T-U Z
G -AB-
SEATING PLANE
DETAIL AD
-AC-
BASE METAL
N
F
8X
D
M_ R
0.20 (0.008)
M
AC T-U Z
0.10 (0.004) AC
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DATUM PLANE -AB- IS LOCATED AT BOTTOM OF LEAD AND IS COINCIDENT WITH THE LEAD WHERE THE LEAD EXITS THE PLASTIC BODY AT THE BOTTOM OF THE PARTING LINE. 4. DATUMS -T-, -U-, AND -Z- TO BE DETERMINED AT DATUM PLANE -AB-. 5. DIMENSIONS S AND V TO BE DETERMINED AT SEATING PLANE -AC-. 6. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE PROTRUSION IS 0.250 (0.010) PER SIDE. DIMENSIONS A AND B DO INCLUDE MOLD MISMATCH AND ARE DETERMINED AT DATUM PLANE -AB-. 7. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. DAMBAR PROTRUSION SHALL NOT CAUSE THE D DIMENSION TO EXCEED 0.520 (0.020). 8. MINIMUM SOLDER PLATE THICKNESS SHALL BE 0.0076 (0.0003). 9. EXACT SHAPE OF EACH CORNER MAY VARY FROM DEPICTION. MILLIMETERS MIN MAX 7.000 BSC 3.500 BSC 7.000 BSC 3.500 BSC 1.400 1.600 0.300 0.450 1.350 1.450 0.300 0.400 0.800 BSC 0.050 0.150 0.090 0.200 0.500 0.700 12_ REF 0.090 0.160 0.400 BSC 1_ 5_ 0.150 0.250 9.000 BSC 4.500 BSC 9.000 BSC 4.500 BSC 0.200 REF 1.000 REF INCHES MIN MAX 0.276 BSC 0.138 BSC 0.276 BSC 0.138 BSC 0.055 0.063 0.012 0.018 0.053 0.057 0.012 0.016 0.031 BSC 0.002 0.006 0.004 0.008 0.020 0.028 12_ REF 0.004 0.006 0.016 BSC 1_ 5_ 0.006 0.010 0.354 BSC 0.177 BSC 0.354 BSC 0.177 BSC 0.008 REF 0.039 REF
J
CE
SECTION AE-AE
X DETAIL AD
GAUGE PLANE
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0.250 (0.010)
H
W
K
Q_
DIM A A1 B B1 C D E F G H J K M N P Q R S S1 V V1 W X
-T-, -U-, -Z-
EE EE EE EE
MC10EP105, MC100EP105
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer.
PUBLICATION ORDERING INFORMATION
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MC10EP105/D

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